Semiconductor integrated circuits (ICs) typically utilize a number of passive components to fulfill various functions such as capacitive coupling and decoupling, resistive pull-up and pull-down, resistive voltage division, and resistive current limiting. These passive components are usually discrete components attached to an interconnection medium, such as a printed circuit board, in close proximity to an associated IC package. Interconnections between the integrated circuit and the passive components are effected by metalized conductors on the printed circuit board.
Current trends in semiconductor device technology have evolved complete functions as well as multiple functions in IC and very large scale integrated circuit (VLSI) packages. Such trends have resulted in a substantial decrease in the overall size of the physical package containing these functional circuits. This, of course, has the desirable affect of smaller and lighter end products. Further decreases in the overall size of these packages may be achieved by reducing the area of the interconnection media that is utilized by the passive components. One way to partly accomplish this, that is presently in use, is to place a multilayer ceramic decoupling capacitor directly under the IC chip inside the IC package. The capacitor is directly wired to appropriate terminals within the package. While this structure is effective in saving space, it does not permit flexibility in use of the passive component with a particular integrated circuit. That is, the passive component is hard wired to the IC in a particular way prior to completing fabrication of the IC package and may not be altered later for an application requiring a different arrangement. Further, since the available space directly under the IC chip in a typical package is quite limited, so is the usefulness of this space for housing multiple passive components.
What is needed, is a structure whereby multiple passive components are disposed on, or in, the IC package rather than on the interconnection medium and arranged so that they may be selectively interconnected to the IC package leads at the time of assembly to the interconnection medium.